Resource Utilization for Audio Formatter v1.0 |
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Resource Utilization for Audio Formatter v1.0
Vivado Design Suite Release 2022.2
Interpreting the results
This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings. Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite. The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true The frequencies used for clock inputs are stated for each test case. LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory. Default Vivado Design Suite 2022.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design. Zynq UltraScale+ Part Information Configuration Parameters Resource Utilization Device Package Speed Grade Configuration Name C_INCLUDE_S2MM C_MAX_NUM_CHANNELS_S2MM C_PACKING_MODE_S2MM C_S2MM_DATAFORMAT C_INCLUDE_MM2S C_MAX_NUM_CHANNELS_MM2S C_PACKING_MODE_MM2S C_MM2S_DATAFORMAT C_MM2S_ADDR_WIDTH C_S2MM_ADDR_WIDTH Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status xczu9eg ffvb1156 2 test_zuplus_wMM2S_w2CH_w55BAW_INTRLVD_wPCM2AES 0 2 0 1 1 2 0 3 55 64 aud_mclk=99 m_axis_mm2s_aclk=100 s_axi_lite_aclk=100 945 1799 0 0 0 PRODUCTION 1.30 05-15-2022 xczu9eg ffvb1156 2 test_zuplus_wMM2S_w2CH_w55BAW_NON_INTRLVD_wPCM2AES 0 2 0 1 1 2 1 3 55 64 aud_mclk=99 m_axis_mm2s_aclk=100 s_axi_lite_aclk=100 1245 2115 0 0 0 PRODUCTION 1.30 05-15-2022 xczu9eg ffvb1156 2 test_zuplus_wMM2S_w4CH_w55BAW_NON_INTRLVD_wPCM2AES 0 2 0 1 1 4 1 3 55 64 aud_mclk=99 m_axis_mm2s_aclk=100 s_axi_lite_aclk=100 1598 2448 0 0 0 PRODUCTION 1.30 05-15-2022 xczu9eg ffvb1156 2 test_zuplus_wMM2S_w8CH_w55BAW_NON_INTRLVD_wPCM2AES 0 2 0 1 1 8 1 3 55 64 aud_mclk=99 m_axis_mm2s_aclk=100 s_axi_lite_aclk=100 2482 3123 0 0 0 PRODUCTION 1.30 05-15-2022 xczu9eg ffvb1156 2 test_zuplus_wS2MM_w2CH_w39BAW_INTRLVD_wAES2PCM 1 2 0 0 0 2 0 3 64 39 s_axi_lite_aclk=100 s_axis_s2mm_aclk=100 1054 2102 0 0 0 PRODUCTION 1.30 05-15-2022 xczu9eg ffvb1156 2 test_zuplus_wS2MM_w2CH_w39BAW_NON_INTRLVD_wAES2PCM 1 2 0 1 0 2 0 3 64 39 s_axi_lite_aclk=100 s_axis_s2mm_aclk=100 1146 2139 0 0 0 PRODUCTION 1.30 05-15-2022 xczu9eg ffvb1156 2 test_zuplus_wS2MM_w4CH_w39BAW_NON_INTRLVD_wAES2PCM 1 4 0 1 0 2 0 3 64 39 s_axi_lite_aclk=100 s_axis_s2mm_aclk=100 1313 2407 0 0 0 PRODUCTION 1.30 05-15-2022 xczu9eg ffvb1156 2 test_zuplus_wS2MM_w8CH_w39BAW_NON_INTRLVD_wAES2PCM 1 8 0 1 0 2 0 3 64 39 s_axi_lite_aclk=100 s_axis_s2mm_aclk=100 1665 2939 0 0 0 PRODUCTION 1.30 05-15-2022 COPYRIGHTCopyright 2022 Xilinx, Inc. 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